The invention relates generally to data processing systems, and more particularly to a shared bus non-sequential data ordering method and apparatus for a data processing system.
Data processing or computer systems typically include a shared data path known as a bus. The bus connects bus units such as processors, memories, and storage devices. Data is transferred between bus units via the bus. The speed at which data is transferred on the bus is an important component of the performance of the computer system.
Requirements for increased data transfer speed on the bus are fueled by an increase in the number of instructions that processors can execute and the speed at which the processors can execute instructions. With the advent of integration technologies of well over one million transistors on a chip and increasing, it is now possible to build superscalar and VLIW (very long instruction word) processors. These processors often execute more than one instruction per cycle, which increases the requirements for large amounts of data to be transferred to and from memory or storage. In addition to the increased integration density of processors, processor speeds are increasing faster than memory access times, and even beyond the time of flight for signals on a bus. This speed mismatch also increases the requirement for large amounts of data to be transferred.
To satisfy these growing requirements for large amounts of data, the speed of the bus needs to be increased. The speed at which a shared bus can transfer data is determined in part by the physical length of the bus, the load on the bus, and the minimum transfer amount (also called the bus width or bus size). The physical length of the bus is simply the length of the connection between bus units. The greater the physical length of the bus, the slower the bus will be. The load is the impedance of one wire of the bus as seen by the driver. The greater the load, the slower the bus will be. The load on the bus is determined by the number of bus units on the bus and the load presented by each bus unit. The minimum transfer amount is the amount of data that is transferred across the bus at one time. The larger the minimum transfer amount, the faster the speed of the data transfer will be. To satisfy the requirements of modern processors, the desired minimum transfer size on the bus that the processor or its cache requires is increasing from four or eight bytes to sixteen or thirty-two bytes and beyond.
Unfortunately it is not always possible to merely increase the size of the minimum transfer in order to increase the bus transfer speed because the size of the minimum transfer is limited by physical constraints. These physical constraints include: the number of I/O pins on chips, chip modules, and card connectors; the wiring constraints of chips, cards, and multi chip modules; and the cost of wide buses. As integrated circuits become more dense and provide the capability of more and more data throughput, they are surpassing the ability of modules and cards to provide the data throughput needed. Even if the technology exists to use the I/O capabilities of chips, it can be cost prohibitive, forcing the use of older, more cost effective packaging technologies to be competitive in the marketplace.
Thus, because of the physical and cost constraints, a complex computer system may have many buses of varying sizes. For example, the cache data bus may be wider than the main store data bus. When two buses of different sizes are connected, the transfer size of one bus must be converted to the transfer size of the other bus. To accomplish this, when converting from a larger transfer size to a smaller transfer size, two or more sub-transfers are required to make up the minimum transfer size. Existing conversion methods use sequential data ordering where each byte is in sequential order with its neighbor on the data bus. For example, when converting from a larger transfer size to a smaller transfer size, the first part of the total width is transferred, then the second part, then the third part, and so on, until the conversion is completed. U.S. Pat. No. 5,243,701 is an example of a memory sub-system that has the capability to work on an eight bit or sixteen bit bus using sequential data ordering.
These existing conversion methods have a problem in that they cause increased loading, which lowers performance, when multiple chips interface to the bus. With the need for wide minimum transfers to increase bus speed, often there will be multiple chips interfacing to the bus. Each of these chips would receive a portion of the data transferred, and there will be more than one chip load on the bus. An example of multiple chips connected to the data bus could be four DRAM controller chips each controlling four bytes of DRAMs to provide a minimum transfer size of sixteen bytes. Another example is four cache controller chips that contain the cache for four bytes of data would also provide a minimum transfer size of sixteen bytes.
Advances in integrated circuits and processor design are creating a new set of problems for the designers of shared busses. The very wide minimum data transfer required by these latest processors and their reduced cycle time pushes the shared bus designer to transfer more data in less time than ever before. When the shared bus width is less than the required minimum transfer, the requested data must be transferred in two or more sub-transfers. To keep the bus operating at the cycle time of the processor the designer must also reduce loading on the bus. With the need for the wide minimum transfer, often there will be multiple chips interfacing to the bus. If the designer uses the current art to convert the minimum required transfer size to the actual bus width there will be extra loading on the bus, thereby reducing its speed. The shared bus non-sequential data ordering method and apparatus that follows provides significant improvement over the prior art in balancing the needs and constraints of the system.
It is a principal object of the present invention to provide a shared bus non-sequential data ordering method and apparatus that overcomes many of the disadvantages of prior art arrangements by enabling reduced bus loading and improved performance of the bus
The objects and advantages of the present invention are achieved by a shared bus non-sequential data ordering method and apparatus. First, a maximum bus width value and a minimum transfer value are identified. Second, a minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. Third, a bus unit having a maximum number of chips to receive and/or send data is identified. Finally, during each data sub-transfer, a corresponding predefined word is transferred to or from each of the chips of the bus unit identified with the maximum number of chips on the bus.